The present invention generally relates to a phase-locked loop (PLL), and more particularly to a circuit for detecting a phase-locked state of a PLL synthesizer circuit. More specifically, the present invention is concerned with a pulse width detecting circuit suitable for detecting the phase-locked state of the PLL synthesizer circuit.
Recently, a PLL synthesizer circuit is widely used in various communication systems. In the field of communication systems, there is a need to provide a digitized phase lock detecting circuit in order to make the PLL synthesizer circuit compact and avoid an adjustment operation thereon.
Referring to FIG. 1, there is illustrated a basic configuration of a PLL synthesizer circuit. A crystal oscillator 1 generates a signal SGI having an inherent frequency based on a vibration of a built-in crystal vibration element. A reference frequency divider 2 receives the signal SG1 and divides the frequency thereof to thereby generate a reference signal SG2 having an appropriate frequency lower than the frequency of the signal SG1. The reference signal SG2 generated and output by the reference frequency divider 2 is input to a phase comparator 3.
FIG. 2 is a circuit diagram of the phase comparator 3. As shown, the phase comparator 3 is composed of NAND circuits 3a, an inverter 3b, a P-channel MOS transistor 3c and an N-channel MOS transistor 3d. The phase comparator 3 has two input terminals Ti1 and Ti2, and two output terminals To1 and To2. The reference signal SG2 is applied to the input terminal Ti1, and a signal SG3 generated by a comparison frequency divider 6 is applied to the input terminal Ti2. The reference signal SG2 and the signal SG3 respectively have waveforms as shown in FIG. 3. In response to the reference signal SG2 and the signal SG3, the phase comparator 3 outputs signals SG4 and SG5 to the output terminals To1 and To2, respectively. The signals SG4 and SG5 are based on the phase difference between the reference signal SG2 and the signal SG3. The signal SG4 is input to a phase lock detecting circuit 100, and the signal SG5 is input to a lowpass filter (LPF) 4.
The lowpass filter 4 smooths the signal SG5 of the phase comparator 3 and outputs a direct-current voltage signal SG6, which is then input to a voltage-controlled oscillator (VCO) 5. The voltage-controlled oscillator 5 varies the oscillation frequency of a signal SG7 on the basis of the direct-current voltage of the signal SG6. The signal SG7 is input to the comparison frequency divider 6, which divides the frequency of the signal SG7 and thereby generates the aforementioned signal SG3.
A digitized structure of the phase lock detecting circuit 100 is illustrated in FIG. 4. The reference frequency divider 2 is composed of a plurality of frequency dividers ql-qn connected in series. The signal SGI generated and output by the crystal oscillator 1 is input to the frequency divider ql of the first stage. The frequency dividers ql-qn divide the frequencies of the respective input signals, and generate respective output signals having frequencies equal to 1/2 of the respective input signals. When the frequency divider qk generates an output signal SGqk, as shown in FIG. 5, the frequency divider qk+1 generates an output signal SGqk+1 having a frequency equal to half the frequency of the output signal SGqk. In this way, the frequency divider qm generates an output signal SGqm.
The input terminal Ti1 of the phase comparator 3 is supplied with, as the reference signal SG2, the output signal SGqm of the frequency divider qm. The phase comparator 3 outputs the signal SG4 based on the phase difference between the reference signal SG2 and the signal SG3 generated and output by the comparison frequency divider 6.
The phase lock detecting circuit 100 is composed of a two-input AND circuit 7, an inverter 8, a D-type flip-flop 9, an RS-type flip-flop 10, a two-input OR circuit 11 and a two-input AND circuit 12. The signal SG4 generated and output by the phase comparator 3 is applied to one of the two input terminals of the AND circuit 7, and the output signal SGqk+1 of the frequency divider qk+1 is applied to the other input terminal of the AND circuit 7. Thus, as shown in FIG. 5, when the signal SG4 from the phase comparator 3 has a pulse width greater than that of the output signal SGqk+1 of the frequency divider qk+1, the AND circuit 7 outputs a signal SG8 having a high level. The signal SG8 thus generated is input to a terminal D of the D-type flip-flop 9.
The D-type flip-flop 9 is supplied with, as a clock signal, the output signal SGqk of the frequency divider qk. The D-type flip-flop 9 generates a signal SG9 from the clock signal as well as the signal SG8 from the AND circuit 7, as shown in FIG. 5. That is, the output signal SG9 rises when the signal SGqk output from the frequency divider qk falls in a state where the signal SG8 from the AND circuit 7 is at the high level, and falls in response to the next fall of the signal SGqk. The signal SG9 thus generated is drawn from a terminal Q of the D-type flip-flop 9 and then input to a terminal S of the RS-type flip-flop 10.
The RS-type flip-flop 10 outputs, as a phase unlock detection signal, a signal SG10 at the high level in accordance with the high-level output signal SG9. When the high-level signal SG10 is generated, the oscillation frequency of the voltage-controlled oscillator 5 is out of the phase-locked state (in the phase-unlocked state). As the phase and frequency of the signal SG3 output by the comparison frequency divider 6 become close to those of the signal SG2 output by the reference frequency divider 2 due to the function of the PLL synthesizer circuit, the pulse width of the signal SG4 output by the phase comparator 3 decreases. Then, the output signal SG10 of the RS-type flip-flop 10 is switched to the low level and the PLL synthesizer circuit is restored to the phase locked state. A signal SG11 for resetting the RS-type flip-flop 12 is generated by the AND circuit 12, which receives the output signals of the frequency dividers qn-1 and qn. The OR circuit 11 receives the signal SG9 and an inverted version of the signal SG10, and outputs an OR operation result thereon to the frequency dividers qn-1 and qn. The pulse width of the signal SG10 is defined by the signal SG11. It is possible to adjust the pulse width of the signal SG10 by supplying the AND circuit 12 with the signals of different frequency dividers.
It should be noted that the waveform diagram of FIG. 5 is illustrated without taking into account an operational delay time caused by the frequency dividers ql-qn connected in series. A slight delay time takes place until each of the frequency dividers starts to operate in response to the output signal of the immediately previous frequency divider. Such a slight delay time is accumulated. An accumulated delay time causes the following problems. As shown in FIG. 6, if there is a slight delay time t between the signal SGqk of the frequency divider qk and the signal SGqm of the frequency divider qm, the phase comparator 3 outputs the signal SG4 having a small pulse width. In the case where the signal SG10 maintained at the low level is output, as the phase lock detection signal, from the RS-type flip-flop 10, there is a possibility that the signal SG4 having a small pulse width passes through the AND circuit 7, and is output as it is, as the signal SG8. Then, the signal SG8 having the small pulse width causes the D-type flip-flop 9 to output the high-level signal SG9. Thus, the RS-type flip-flop 10 outputs the high-level signal SGIO, as the phase unlock detection signal irrespective of whether or not the PLL synthesizer circuit is in the phase-locked state. The signal SG10 is used, for example, in a communication device capable of communicating with another party at an arbitrary frequency. When the phase unlock detection signal is generated irrespective of whether or not the PLL synthesizer circuit is correctly in the phase-locked state, the established communication channel will be destroyed.